Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional sample-and-hold (S/H) circuit with non-linear compensation. Circuit 100 generally comprises an S/H circuit 104, MOS capacitors C1 to CN, a current source 106, and a voltage divider 108. In operation, both the S/H circuit 104 and MOS capacitor C1 to CN receive the input signal IN, and the S/H circuit generates output signal OUT. Each of the MOS capacitors C1 to CN also receive a respective control voltage V1 to VN from divider 108 (which is supplied by current source 106 and generally comprises resistors R1 through RM coupled in series with one another). Application of these control voltages V1 to VN to MOS capacitors C1 to CN control the capacitance versus voltage profiles of capacitors C1 to CN so as to allow the current to be drawn (which is depending on the amplitude of signal IN). This current can then be used to compensate for the input dependent amplitude current draw by a downstream ADC or sub-ADC, reducing third harmonic content.
Circuit 100, however, is sensitive to both temperature and process variations. This sensitivity is primarily due to the fact that the control voltages V1 to VN are generated at some nominal process corner, remaining relatively constant, whereas the threshold voltage of MOS capacitors C1 to CN varies with temperature and process. Additionally, because the capacitance profile of the MOS capacitors C1 to CN depends on the difference between the gate-source voltages and threshold voltage, the variation of the gate-source voltages can make circuit 100 sensitive to the common mode of signal IN. Since the nonlinear current draw from a downstream ADC is generally constant with respect to temperature and process variations, the effectiveness of circuit 100 can be limited.
Therefore, there is a need for improved circuit.